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Space Education Catalogue

Courses

Stage - Système de haut niveau (HLS) pour system on chip

Course Details

Objectives : Providing hardware acceleration, system security and product scalability, FPGA circuits are now an essential component of embedded electronic devices. To meet the ever-shorter cycles of products placed on the market, it is becoming essential to master its relative complexity through the expert use of (new) high-level description tools (High-level synthesis, or HLS). At the end of this training, participants will be able to master the entire design flow of a complex digital system using an HLS language.

Public concerned : Engineers responsible for designing, developing or maintaining systems on chip based on FPGAs.

Prerequisites : Digital electronics: FPGA and hardware description language (VHDL, Verilog, etc.).
Microprocessor: architecture and low-level programming language (C language).
The “System on Chip (SoC): co-design of software and hardware embedded on FPGA” course is an excellent entry point for this training.
Computer science: algorithms is a second possible entry point for this training.

Duration and terms : 21 h

Dedicated web site : https://fc.sorbonne-universite.fr/nos-offres/synthese-de-haut-niveau-hls-pour-system-on-chip/

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